An integral analog-to-digital converter (ADC) using a time-to-digital converter (TDC) has been proposed. This type of integral ADC performs fine A/D conversion using TDC in addition to coarse A/D conversion using a ramp signal to increase the resolution of A/D conversion and speed up the A/D conversion.
However, TDC requires a high-speed clock signal. Thus, if a high-speed clock signal is supplied to TDC while performing coarse A/D conversion using a ramp signal, a consumption power increases.
Moreover, different clock signals are used for coarse A/D conversion using a ramp signal and fine A/D conversion using TDC. Thus, A/D conversion performance may be lowered due to phase difference between both clock signals.